1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device consisting of twin memory cells, each including one word gate and two non-volatile memory elements controlled by two control gates, as well as to a method of actuating such a non-volatile semiconductor memory device.
2. Description of the Related Art
A known non-volatile semiconductor memory device that is capable of electric writing (programming) and erasing is MONOS (metal-oxide-nitride-oxide-semiconductor or -substrate) type, where a gate insulating layer between a channel and a gate is a laminate of a silicon oxide film, a silicon nitride film, and a silicon oxide film and the silicon nitride film traps electric charges.
The MONOS-type non-volatile semiconductor memory device is disclosed in a reference Y. Hayashi et al, 2000 Symposium on VLSI Technology Digest of Technical Papers p.122-123). This cited reference describes a twin MONOS flash memory cell having one word gate and two non-volatile memory elements (also be referred to as MONOS memory elements or cells) controlled by two control gates. Namely one flash memory cell has two trap sites of electric charges.
The MONOS-type non-volatile semiconductor memory device includes multiple twin MONOS flash memory cells of such structure, which are arrayed in rows and columns.
This non-volatile semiconductor memory device (flash memory) carries out data reading, writing (programming), and erasing operations. The data programming operation and the data reading operation are typically performed by the unit of 1 byte (8 bits) or by the unit of 1 word (16 bits). The procedure of the data programming operation or the data reading operation simultaneously selects 1 byte of or 1 word of non-volatile memory elements and simultaneously writes or reads data into or from these selected non-volatile memory elements (selected cells). The respective bit signals corresponding to these selected cells are input and output via I/O lines.
In the field of semiconductor memory devices, with the increased storage capacity and the enhanced access speed, the twin MONOS-type non-volatile semiconductor memory device consisting of twin MONOS flash memory cells is required to have the high access speed. In order to fulfill this requirement and enhance the read and write access speed, most semiconductor memory devices have a xe2x80x98page mode readingxe2x80x99 function to read data in a page mode for high-speed reading and a xe2x80x98page buffer writingxe2x80x99 function to write data into a page buffer for high-speed writing.
In the case of reading data from the semiconductor memory device by the xe2x80x98page mode readingxe2x80x99 function, in response to specification of a row address in the semiconductor memory device, all the contents of multiple memory elements or memory cells corresponding to the row address are registered in a temporary buffer in the semiconductor memory device. As the column address changes, the corresponding data are read from the temporary buffer and are output. The speed of reading data from the temporary buffer is higher than the speed of reading data from the memory cells. The xe2x80x98page mode readingxe2x80x99 function thus attains the high-speed read access.
In the case of writing data into the semiconductor memory device by the xe2x80x98page buffer writingxe2x80x99 function, multiple data of an identical row address but different column addresses are successively input and are registered in the page buffer. The multiple data registered in the page buffer are collectively written into multiple corresponding memory elements. The xe2x80x98page buffer writingxe2x80x99 function, which collectively writes multiple data into the corresponding memory elements, attains the high-speed write access.
In the prior art twin MONOS-type non-volatile semiconductor memory device, however, data are read and write by the unit of 1 byte or by the unit of 1 word, as mentioned previously. Namely the prior art twin MONOS-type non-volatile semiconductor memory device does not have the xe2x80x98page mode readingxe2x80x99 function or the xe2x80x98page buffer writing functionxe2x80x99 and thereby can not attain the sufficiently high access speed.
In order to solve the drawbacks of the prior art technique discussed above, the object of the present invention is to provide a non-volatile semiconductor memory device of twin memory cells having access functions to allow for reading in a page mode and writing into a page buffer, thus enhancing the access speed.
In order to attain at least part of the above and the other related objects, a first application of the present invention is directed to a non-volatile semiconductor memory device, which includes: a memory cell array having multiple twin memory cells arrayed at least in a row direction, where each of the twin memory cells has one word gate, a first non-volatile memory element controlled by a first control gate, and a second non-volatile memory element controlled by a second control gate; a word line shared by the word gates of the multiple twin memory cells arrayed in the row direction; multiple bit lines, each of which is provided for every pair of adjoining twin memory cells in the row direction and is shared by the first non-volatile memory element included in one twin memory cell of the twin memory cell pair and by the second non-volatile memory element included in the other twin memory cell to be extended in a column direction; multiple control gate lines, each of which is provided for every pair of adjoining twin memory cells in the row direction and is shared by the first control gate of the first non-volatile memory element included in one twin memory cell of the twin memory cell pair and by the second control gate of the second non-volatile memory element included in the other twin memory cell to be extended in the column direction; an access control circuit that regulates operations of the word line, the multiple bit lines, and the multiple control gate lines to control a reading operation of information; and a detection circuit that detects the information read via the multiple bit lines.
In the non-volatile semiconductor memory device of the first application, in the case of reading information from the second non-volatile memory element of an (i)-th twin memory cell and from the first non-volatile memory element of an (i+1)-th twin memory cell in the row direction, where i is an integer of not less than 1, the access control circuit sets a reading word line-selecting voltage to the word line connecting with the word gate of the (i)-th twin memory cell and with the word gate of the (i+1)-th twin memory cell. The access control circuit also sets a reading control gate voltage to the second control gate of the second non-volatile memory element of the (i)-th twin memory cell via an (i)-th control gate line connecting with the second control gate. The access control circuit further sets an override voltage to the first control gate of the first non-volatile memory element of the (i)-th twin memory cell via an (ixe2x88x921)-th control gate line connecting with the first control gate, while setting an override voltage to the second control gate of the second non-volatile memory element of the (i+1)-th twin memory cell via an (i+1)-th control gate line connecting with the second control gate.
The detection circuit senses an (ixe2x88x921)-th bit line connecting with the first non-volatile memory element of the (i)-th twin memory cell, so as to detect an electric current running between the (ixe2x88x921)-th bit line and an (i)-th bit line connecting with the second non-volatile memory element of the (i)-th twin memory cell, via the second non-volatile memory element of the (i)-th twin memory cell. The detection circuit also senses an (i+1)-th bit line connecting with the second non-volatile memory element of the (i+1)-th twin memory cell, so as to detect an electric current running between the (i+1)-th bit line and the (i)-th bit line connecting with the first non-volatile memory element of the (i+1)-th twin memory cell, via the first non-volatile memory element of the (i+1)-th twin memory cell. The detection circuit thereby reads a piece of information stored in the second non-volatile memory element of the (i)-th twin memory cell together with a piece of information stored in the first non-volatile memory element of the (i+1)-th twin memory cell.
The structure of the non-volatile semiconductor memory device as the first application enables the information to be collectively read from the second non-volatile memory element included in the (i)-th twin memory cell and from the first non-volatile memory element included in the (i+1)-th twin memory cell in the row direction.
In one preferable embodiment of the first application, the non-volatile semiconductor memory device further includes a selection circuit that successively selects the two pieces of information read together by the detection circuit.
The successive selection and output of the collectively read information allows two pieces of information per page to be read in the page mode. The arrangement of the first application accordingly gives the non-volatile semiconductor memory device of twin memory cells that can read data in the page mode, thus enhancing the access speed.
A second application of the present invention is directed to a non-volatile semiconductor memory device, which includes: a memory cell array having multiple twin memory cells arrayed at least in a row direction, where each of the twin memory cells has one word gate, a first non-volatile memory element controlled by a first control gate, and a second non-volatile memory element controlled by a second control gate; a word line shared by the word gates of the multiple twin memory cells arrayed in the row direction; multiple bit lines, each of which is provided for every pair of adjoining twin memory cells in the row direction and is shared by the first non-volatile memory element included in one twin memory cell of the twin memory cell pair and by the second non-volatile memory element included in the other twin memory cell to be extended in a column direction; multiple control gate lines, each of which is provided for every pair of adjoining twin memory cells in the row direction and is shared by the first control gate of the first non-volatile memory element included in one twin memory cell of the twin memory cell pair and by the second control gate of the second non-volatile memory element included in the other twin memory cell to be extended in the column direction; an access control circuit that regulates operations of the word line, the multiple bit lines, and the multiple control gate lines to control a reading operation of information; and a detection circuit that detects the information read via the multiple bit lines.
In the non-volatile semiconductor memory device of the second application, the memory cell array is divided into m memory blocks in the row direction, where m is an integer of not less than 1. Each of the memory blocks is divided into n column blocks in the row direction, where n is an integer of not less than 2.
In the non-volatile semiconductor memory device of the second application, in the case of reading information from the second non-volatile memory element of an (i)-th twin memory cell and from the first non-volatile memory element of an (i+1)-th twin memory cell in the row direction in each of the column blocks, where i is an integer of not less than 1, the access control circuit sets a reading word line-selecting voltage to the word line connecting with the word gate of the (i)-th twin memory cell and with the word gate of the (i+1)-th twin memory cell. The access control circuit also sets a reading control gate voltage to the second control gate of the second non-volatile memory element of the (i)-th twin memory cell via an (i)-th control gate line connecting with the second control gate. The access control circuit further sets an override voltage to the first control gate of the first non-volatile memory element of the (i)-th twin memory cell via an (ixe2x88x921)-th control gate line connecting with the first control gate, while setting an override voltage to the second control gate of the second non-volatile memory element of the (i+1)-th twin memory cell via an (i+1)-th control gate line connecting with the second control gate.
The detection circuit senses an (ixe2x88x921)-th bit line connecting with the first non-volatile memory element of the (i)-th twin memory cell, so as to detect an electric current running between the (ixe2x88x921)-th bit line and an (i)-th bit line connecting with the second non-volatile memory element of the (i)-th twin memory cell, via the second non-volatile memory element of the (i)-th twin memory cell. The detection circuit also senses an (i+1)-th bit line connecting with the second non-volatile memory element of the (i+1)-th twin memory cell, so as to detect an electric current running between the (i+1)-th bit line and the (i)-th bit line connecting with the first non-volatile memory element of the (i+1)-th twin memory cell, via the first non-volatile memory element of the (i+1)-th twin memory cell. The detection circuit thereby reads a piece of information stored in the second non-volatile memory element of the (i)-th twin memory cell together with a piece of information stored in the first non-volatile memory element of the (i+1)-th twin memory cell.
Like the non-volatile semiconductor memory device of the first application, the structure of the non-volatile semiconductor memory device as the second application enables (2xc2x7n) pieces of information to be read collectively from the two non-volatile memory elements of n column blocks in each memory block.
In one preferable embodiment of the second application, the non-volatile semiconductor memory device further includes a selection circuit that is provided in each of the memory blocks and successively selects (2xc2x7n) pieces of information read together by the detection circuit.
The successive selection and output of the collectively read information allows (2xc2x7n) pieces of information per page to be read in the page mode. The arrangement of the second application accordingly gives the non-volatile semiconductor memory device of twin memory cells that can read data in the page mode, thus enhancing the access speed.
In the structure of the second application, the column block includes four twin memory cells arrayed in the row direction, and the memory block includes (4xc2x7n) twin memory cells arrayed in the row direction.
A third application of the present invention is directed to a non-volatile semiconductor memory device, which includes: a memory cell array having multiple twin memory cells arrayed at least in a row direction, where each of the twin memory cells has one word gate, a first non-volatile memory element controlled by a first control gate, and a second non-volatile memory element controlled by a second control gate; a word line shared by the word gates of the multiple twin memory cells arrayed in the row direction; multiple bit lines, each of which is provided for every pair of adjoining twin memory cells in the row direction and is shared by the first non-volatile memory element included in one twin memory cell of the twin memory cell pair and by the second non-volatile memory element included in the other twin memory cell to be extended in a column direction; multiple control gate lines, each of which is provided for every pair of adjoining twin memory cells in the row direction and is shared by the first control gate of the first non-volatile memory element included in one twin memory cell of the twin memory cell pair and by the second control gate of the second non-volatile memory element included in the other twin memory cell to be extended in the column direction; an access control circuit that regulates operations of the word line, the multiple bit lines, and the multiple control gate lines to control a reading operation of information; a buffer circuit that stores in advance multiple pieces of information; and a bit line actuation circuit that is driven to write the information stored in the buffer circuit via the multiple bit lines.
In the non-volatile semiconductor memory device of the third application, the memory cell array is divided into m memory blocks in the row direction, where m is an integer of not less than 1. Each of the memory blocks is divided into n column blocks in the row direction, where n is an integer of not less than 2,
In the non-volatile semiconductor memory device of the third application, in the case of writing the information into the second non-volatile memory element of an (i)-th twin memory cell in the row direction in each of the column blocks, where i is an integer of not less than 1, the access control circuit sets a programming word line-selecting voltage to the word line connecting with the word gate of the (i)-th twin memory cell. The access control circuit also sets a programming control gate voltage to the second control gate of the second non-volatile memory element of the (i)-th twin memory cell via an (i)-th control gate line connecting with the second control gate. The access control circuit further sets a programming bit line voltage, which is supplied from the bit line actuation circuit, to an (i)-th bit line connecting with the second non-volatile memory element of the (i)-th twin memory cell.
The non-volatile semiconductor memory device of the third application enables information to be written into one non-volatile memory element in each of n column blocks in each memory block. Namely the n pieces of information stored in advance in the buffer circuit can be written collectively. The arrangement of the third application accordingly gives the non-volatile semiconductor memory device of twin memory cells that can write data into the page buffer, thus enhancing the access speed.
A fourth application of the present invention is directed to a method of actuating a non-volatile semiconductor memory device. Here the non-volatile semiconductor memory device includes: a memory cell array having multiple twin memory cells arrayed at least in a row direction, where each of the twin memory cells has one word gate, a first non-volatile memory element controlled by a first control gate, and a second non-volatile memory element controlled by a second control gate; a word line shared by the word gates of the multiple twin memory cells arrayed in the row direction; multiple bit lines, each of which is provided for every pair of adjoining twin memory cells in the row direction and is shared by the first non-volatile memory element included in one twin memory cell of the twin memory cell pair and by the second non-volatile memory element included in the other twin memory cell to be extended in a column direction; and multiple control gate lines, each of which is provided for every pair of adjoining twin memory cells in the row direction and is shared by the first control gate of the first non-volatile memory element included in one twin memory cell of the twin memory cell pair and by the second control gate of the second non-volatile memory element included in the other twin memory cell to be extended in the column direction.
In the case of reading information from the second non-volatile memory element of an (i)-th twin memory cell and from the first non-volatile memory element of an (i+1)-th twin memory cell in the row direction, where i is an integer of not less than 1, the method of the fourth application includes the steps of: setting a reading word line-selecting voltage to the word line connecting with the word gate of the (i)-th twin memory cell and with the word gate of the (i+1)-th twin memory cell; setting a reading control gate voltage to the second control gate of the second non-volatile memory element of the (i)-th twin memory cell via an (i)-th control gate line connecting with the second control gate; and setting an override voltage to the first control gate of the first non-volatile memory element of the (i)-th twin memory cell via an (ixe2x88x921)-th control gate line connecting with the first control gate, while setting an override voltage to the second control gate of the second non-volatile memory element of the (i+1)-th twin memory cell via an (i+1)-th control gate line connecting with the second control gate. The method also includes the step of sensing an (ixe2x88x921)-th bit line connecting with the first non-volatile memory element of the (i)-th twin memory cell, so as to detect,an electric current running between the (ixe2x88x921)-th bit line and an (i)-th bit line connecting with the second non-volatile memory element of the (i)-th twin memory cell, via the second non-volatile memory element of the (i)-th twin memory cell, sensing an (i+1)-th bit line connecting with the second non-volatile memory element of the (i+1)-th twin memory cell, so as to detect an electric current running between the (i+1)-th bit line and the (i)-th bit line connecting with the first non-volatile memory element of the (i+1)-th twin memory cell, via the first non-volatile memory element of the (i+1)-th twin memory cell, thereby reading a piece of information stored in the second non-volatile memory element of the (i)-th twin memory cell together with a piece of information stored in the first non-volatile memory element of the (i+1)-th twin memory cell.
Like the non-volatile semiconductor memory device of the first application, the method of actuating the non-volatile semiconductor memory device as the fourth application enables the information to be collectively read from the second non-volatile memory element included in the (i)-th twin memory cell and from the first non-volatile memory element included in the (i+1)-th twin memory cell in the row direction. This arrangement enhances the access speed of the non-volatile semiconductor device consisting of twin memory cells.
A fifth application of the present invention is directed to a method of actuating a non-volatile semiconductor memory device. Here the non-volatile semiconductor memory device includes: a memory cell array having multiple twin memory cells arrayed at least in a row direction, where each of the twin memory cells has one word gate, a first non-volatile memory element controlled by a first control gate, and a second non-volatile memory element controlled by a second control gate; a word line shared by the word gates of the multiple twin memory cells arrayed in the row direction; multiple bit lines, each of which is provided for every pair of adjoining twin memory cells in the row direction and is shared by the first non-volatile memory element included in one twin memory cell of the twin memory cell pair and by the second non-volatile memory element included in the other twin memory cell to be extended in a column direction; and multiple control gate lines, each of which is provided for every pair of adjoining twin memory cells in the row direction and is shared by the first control gate of the first non-volatile memory element included in one twin memory cell of the twin memory cell pair and by the second control gate of the second non-volatile memory element included in the other twin memory cell to be extended in the column direction. In this non-volatile semiconductor memory device, the memory cell array is divided into m memory blocks in the row direction, where m is an integer of not less than 1. Each of the memory blocks is divided into n column blocks in the row direction, where n is an integer of not less than 2,
In the case of reading information from the second non-volatile memory element of an (i)-th twin memory cell and from the first non-volatile memory element of an (i+1)-th twin memory cell in the row direction in each of the column blocks, where 1 is an integer of not less than 1, the method of the fifth application includes the steps of: setting a reading word line-selecting voltage to the word line connecting with the word gate of the (i)-th twin memory cell and with the word gate of the (i+1)-th twin memory cell; setting a reading control gate voltage to the second control gate of the second non-volatile memory element of the (i)-th twin memory cell via an (i)-th control gate line connecting with the second control gate; and setting an override voltage to the first control gate of the first non-volatile memory element of the (i)-th twin memory cell via an (ixe2x88x921)-th control gate line connecting with the first control gate, while setting an override voltage to the second control gate of the second non-volatile memory element of the (i+1)-th twin memory cell via an (i+1)-th control gate line connecting with the second control gate. The method also includes the step of: sensing an (ixe2x88x921)-th bit line connecting with the first non-volatile memory element of the (i)-th twin memory cell, so as to detect an electric current running between the (ixe2x88x921)-th bit line and an (i)-th bit line connecting with the second non-volatile memory element of the (i)-th twin memory cell, via the second non-volatile memory element of the (i)-th twin memory cell, sensing an (i+1)-th bit line connecting with the second non-volatile memory element of the (i+1)-th twin memory cell, so as to detect an electric current running between the (i+1)-th bit line and the (i)-th bit line connecting with the first non-volatile memory element of the (i+1)-th twin memory cell, via the first non-volatile memory element of the (i+1)-th twin memory cell, thereby reading a piece of information stored in the second non-volatile memory element of the (i)-th twin memory cell together with a piece of information stored in the first non-volatile memory element of the (i+1)-th twin memory cell.
Like the non-volatile semiconductor memory device of the second application, the method of actuating the non-volatile semiconductor memory device as the fifth application enables (2xc2x7n) pieces of information to be read collectively from the two non-volatile memory elements of n column blocks in each memory block. This arrangement enhances the access speed of the non-volatile semiconductor memory device consisting of twin memory cells.
A sixth application of the present invention is directed to a method of actuating a non-volatile semiconductor memory device. Here the non-volatile semiconductor memory device includes: a memory cell array having multiple twin memory cells arrayed at least in a row direction, where each of the twin memory cells has one word gate, a first non-volatile memory element controlled by a first control gate, and a second non-volatile memory element controlled by a second control gate; a word line shared by the word gates of the multiple twin memory cells arrayed in the row direction; multiple bit lines, each of which is provided for every pair of adjoining twin memory cells in the row direction and is shared by the first non-volatile memory element included in one twin memory cell of the twin memory cell pair and by the second non-volatile memory element included in the other twin memory cell to be extended in a column direction; and multiple control gate lines, each of which is provided for every pair of adjoining twin memory cells in the row direction and is shared by the first control gate of the first non-volatile memory element included in one twin memory cell of the twin memory cell pair and by the second control gate of the second non-volatile memory element included in the other twin memory cell to be extended in the column direction. In this non-volatile semiconductor memory device, the memory cell array is divided into m memory blocks in the row direction, where m is an integer of not less than 1. Each of the memory blocks is divided into n column blocks in the row direction, where n is an integer of not less than 2.
In the case of writing the information into the second non-volatile memory element of an (i)-th twin memory cell in the row direction in each of the column blocks, where i is an integer of not less than 1, the method of the sixth application includes the steps of: setting a programming word line-selecting voltage to the word line connecting with the word gate of the (i)-th twin memory cell; setting a programming control gate voltage to the second control gate of the second non-volatile memory element of the (i)-th twin memory cell via an (i)-th control gate line connecting with the second control gate; and setting a programming bit line voltage, which is supplied from the bit line actuation circuit, to an (i)-th bit line connecting with the second non-volatile memory element of the (i)-th twin memory cell.
Like the non-volatile semiconductor memory device of the third application, the method of actuating the non-volatile semiconductor memory device as the sixth application enables the non-volatile semiconductor memory device of twin memory cells to write data into the page buffer, thus enhancing the access speed of the non-volatile semiconductor memory device.
The above and other objects, features, aspects, and advantages of the present invention will become more apparent from the following detailed description of the preferred embodiment with the accompanying drawings.